10 Years of Experience in FPGA/ASIC Front end Design.
• High Speed Digital Design for building very high speed data acquisition and processing platforms.
• Expertise in Xilinx, Altera, Lattice, Actel IDE Tools & FPGAs.
• Block and System level verification based on Test bench, BFM, Regression test
• Strong LAB experience using Ocilloscopes, Logical analyzers and Matlab Simulink Hardware in Loop System Co-Simulations.
• Design and development of Complex Digital IPs in ASIC and SoCs using Synopsys & Cadence Tools.
• Static Timing Analysis and Timing Closure on Logic Designs.
• Configuration Management: SVN, Microsoft-VSS.
• Operating System: Sun Solaris, Linux, Unix, Windows
• Hardware Design: ASIC/SoC & FPGA Design.
• Hardware Descriptive Languages: VHDL, Verilog & SystemVerilog.
• Scripting Languages: TCL/TK, Unix/Solaris shell.
• Bus/Interfaces: PCI Express (PCIe), Gigabit Ethernet, JESD204B, NAND/NOR Flash, Serial Rapid IO (SRIO), TI's OMAP 4, I2S, I2C, SPI, UART, RTC, DSP Interfaces, Microprocessor and peripheral Interfaces.
• Signal Processing: Matlab Simulink Modeling & Coding.
• Programming languages: Exposure to C & C++