Krishna Jandhyam

I am currently working as an Senior Design Engineer (SOC Architect) at Silicon technology prototyping labs, Bangalore Design Labs, Bangalore.

During my tenure in the semiconductor industry, I have gained valuable experience in the entire chip development process, though my primary focus has been the front-end, which is digital IP design along with SOC Architecture and design.

As part of digital IP design, I have designed various IPs such as DMA controller, DDR memory controller, SPI, multi-layer BUS fabrics from scratch, which are being used in various SOCs. In addition to generic IPs, I also have hands on experience on complex IPs such as communication sub-system that supports WiFi and BTLE.

As part of SOC design, I worked on architecture, IP interface definition and integration, timing closure and have also been a part of architecture team for choosing processor, fabric, peripherals and estimating memory requirements that affect FW/SW.

In addition to the architecture and design, I have hands on experience on verification using advanced methodologies such as UVM as well.