prashant gupta

#Good hands on experience in laboratory with EDA tools of Cadence. # Familiar with DRC and LVS errors and solving them. # Performed layouts, post-layout simulations of schematics.# Physical design using SOC encounter. # Timing verification using static timing Analyzer.# Knowledge of PERL-automation for report filtering.# Proficient at Verilog-HDL. # FPGA, ASIC# Worked on 45nm, 90nm and 180nm technology nodes of GPDK.#An year experience in semiconductor industryTo obtain a position as a Physical design/Verification engineer with provision for innovation creativity in a growing and quality-focused organization for getting a right start and quality exposure.