Sagar Shivaram

I have a Master's Degree in Electrical Engineering with a major in Embedded Systems and VLSI. Currently seeking full-time/intern positions in the field of Digital Design, FPGA / ASIC Design.

Strengths: Digital Design, FPGA Design using Verilog HDL, Synthesis, Place and route Netlist using EDA tools, RTL design using FSM, static timing analysis and verification

Skill Set: Altera FPGA, Xilinx FPGA, RTL design, SoC Design, Microprocessors, Microcontrollers, product life cycle

Software Packages: Verilog HDL, C, Embedded C, Object Oriented Programming (OOP) using C++, Shell Scripting, Python Scripting, Matlab, Mathematica, VB.net, ModelSim, Cadence Virtuoso, Magic VLSI, CALP (CAD Tool), PSpice