Sandeep Solanki

I am DFT Engineer currently living in India, working at the Einfochips An Arrow Company. I worked on 7+ chip tapeouts with the responsibility of Scan insertion, pattern generation, and simulation with or without timing, JTAG insertion, and verification, Constraints generation for timing simulations.

I am fluent in Verilog and VHDL. I have hands-on experience in EDA tools Synopsys DFT Compiler, TetraMAX, VCS, Tessent shell, LV Flow for MBIST insertion, Cadence Genus, Modus, Simvision,Cadence Virtuoso, Cadence Innovus, Cadence Abstract, Cadence Liberate, QuestaSIM, Synopsys Design Compiler, Xilinx ISE 14.7, Xilinx VIVADO

I have done Scan Insertion using Synopsys Design compiler, Genus, Pattern generation (ATPG) and validation with timing and without timing, Timing Constraint SDC generation for Scan worked with 5+ global customer projects

In-depth knowledge and experience in ASIC DFT domain. Responsibilities mainly included deciding DFT architecture, SCAN chain implementation, ATPG, simulation timing, and no timing, RTL debug, JTAG_insertion.

I have done the chip tapeout processes of three digital IC’s from RTL Level to GDSII- one SRAM array, one containing Radiation Hardened circuits (tested for TID effects as well), and one on Synchronizer circuits. I have hands-on experience in FPGA boards like Spartan 3E, Spartan 6, Veritex 5, Basys 2, Basys 3.

I hold a Masters in VLSI design from C-DAC Mohali, where my thesis topic was working on various software techniques used to make systems Radiation Hardened. One of the most interesting things I did as a hobby was coding up a game similar to Temple Run using the Spartan 3 FPGA board with VGA interfacing.

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